It has been known that the voltage-blocking capability in a lateral Silicon-On-Insulator (SOI) device structure is usually limited by a peaking of the electric fields on the anode (drain) side. While a thicker buried oxide will result in a higher blocking voltage, an increased oxide layer thickness is further known to correspondingly impede heat dissipation due to its low thermal conductivity. While acceptable for high voltage devices (in the range &gt;500 v), this inefficiency is wholly unacceptable for lower voltage devices, which, have a breakdown voltage of less than or equal to 100 volts.
More specifically, the design of a lateral SOI structure is impacted by three parameters: the SOI layer thickness (T.sub.soi), lateral depletion width (L.sub.bv) at breakdown, and buried oxide thickness (T.sub.box). As those skilled in the art will recognize, the electric field crowding near the anode (drain) can be minimized by using the field-tailoring scheme proposed by researchers at North America Phillips Corporation, New York, N.Y. S. Merchant, E. Arnold, H. Baumgart, S. Mukherjee, H. Pein, and R. Pinker, in their paper "Realization of High Breakdown Voltage (&gt;700 v) In Thin SOI Devices", THIRD INT. SYMP. ON POWER SEMICONDUCTOR DEVICES AND ICS, 1991, pp. 31-35, disclose a linearly-graded lateral dopant profile used to realize a 700 v (0.2-0.3 microns) thin SOI structure at the expense of a two-micron thick buried oxide.
Merchant, et al, in U.S. Pat. No. 5,300,448 also assigned to North American Phillips Corporation discloses a method and thin film transistor having a linear doping profile between the gate and drain regions. The linear doping is achieved by introducing impurities into a thin silicon layer deposited over an oxide which in turn is deposited on a silicon substrate. The impurities are introduced through a mask having a plurality of openings, each of the openings laterally increasing in dimension from that of a preceding opening. The multi-opening mask design permits the formation of a plurality of doped regions of different widths so as to form a doping profile having a minimum doping concentration at one end of the lateral distance and a maximum doping concentration at the other end of the lateral distance.
U.S. Pat. No. 5,246,870 to Merchant is similarly directed to an improvement in a self-passivated high voltage semiconductor device. The semiconductor device has a thinned SOI layer having a linear lateral doping region coated with an oxide layer and a field plate which is part of the gate electrode layer. The lateral linear doping region is formed in the silicon layer by selectively thinning the drift region by local oxidation (LOCOS), leaving a thick top oxide layer over the drift region, and forming a gate region at a side of the top oxide layer. The formed gate region has a gate electrode with a portion extending laterally over a substantial portion of the top oxide layer where the lateral extent of the gate electrode overlies the thin lateral linear doping region. The desired high voltage SOI semiconductor device is achieved using this structure.
Significantly, each of the devices discussed above is designed in accordance with the theory that a lateral linear dopant concentration profile between the cathode (source) and anode (drain) in a SOI device structure will greatly enhance the breakdown voltage. These devices therefore incorporate buried oxide layers having substantial thicknesses as well as long lateral doping gradient distances.
Still further, the devices described above are operative with supply voltages .gtoreq.500 volts. These devices typically require an SOI film thickness of 2000-3000 .ANG. (0.2-0.3 microns), a buried oxide thickness of at least 2 microns and a doping gradient over a lateral distance of 40-50 microns. As known to those skilled in the art, such devices include, for example, AC motor control technology, switching regulator technology, fluorescent light ballast technology, and telecommunications technology.
In these devices, the lateral doping gradient is achieved through the use of elaborate photolithographic schemes. See, for example, the publication of R. Stengl and U. G. Sel "Variation Of Lateral Doping A New Concept To Avoid High Voltage Breakdown Of Planar Junctions", IDEM TECH. DIG., 1985, pp. 154-157.
As discussed above, for "lower voltage" devices, i.e. those having a breakdown voltage of .ltoreq.100 volts, thick oxide layers are unacceptable from an efficiency standpoint because an increase in the layer thickness is inversely proportional to a decrease in heat dissipation. Such "lower voltage" devices include, for example, numerous applications of digital technology, bipolar linear technology, automotive technology, linear regulator technology, display technology, and telecommunications technology.
Consequently, a need has developed for an improved "low voltage", high performance, lateral Silicon-On-Insulator (SOI) power device and a method of fabricating such power devices.